A semiconductor circuit or logic device may be designed for any of a wide variety of applications. Typically, the device includes logic circuitry to receive, manipulate or store input data, and the same or modified data is subsequently generated at an output terminal of the device. Depending on the type of logic device or the circuit environment in which the device is used, the device may include a regulator that provides an internal power signal that is independent of fluctuations of an external power signal.
A dynamic random access memory (DRAM), formed as an integrated circuit, is an example of such a semiconductor circuit or logic device having a regulator. Conventionally, the DRAM receives an external power signal (V.sub.CCX) having a voltage intended to maintain a voltage level (or range), for example, of 5 volts measured relative to common or ground. Internal to the DRAM, the regulator maintains an internal power signal (V.sub.CCR) at a designated level, for example, of 3.3 volts. Ideally, V.sub.CCR linearly tracks V.sub.CCX from zero volts to the designated level at which point V.sub.CCR remains constant as V.sub.CCX continues to increase in voltage or fluctuate above this level.
A number of previously implemented semiconductor power regulation circuits use a feedback-controlled p-channel transistor at the output of a control circuit, wherein the p-channel transistor is modulated once V.sub.CCX reaches the internal operating voltage level, at which point V.sub.CCR remains constant as described above. This approach is disadvantageous, however, because the feedback-controlled p-channel transistor acts in a manner similar to an operational amplifier whereby a substantial amount of current may be consumed during normal operation.
One known approach for mitigating this problem is to implement the control circuit at the input of the p-channel transistor with a low-power standby mode. In this mode, the larger p-channel transistor is deactivated when the integrated circuit is not in use so as to limit the excessive drain of drive current by the feedback-controlled p-channel transistor. Despite this limitation on current consumption, it is still desirable to reduce the overall level of current consumption. This is especially true for integrated circuit applications in which the integrated circuit is seldom not in use, in which case the beneficial contribution of the standby mode is nominal at best. Moreover, the standby approach introduces a delay to the operation of the integrated circuit, for example, during the transition from standby to normal operation. For fast-responding integrated circuits, such an additional delay is undesirable and often unacceptable.
U.S. Pat. No. 5,552,740 (the Casper patent) issued to Stephen L. Casper on Sep. 3, 1996 and is assigned to Micron Technology, Inc. The Casper patent describes an alternative to the more conventional feedback-controlled p-channel transistor-based regulator. Specifically, Casper describes a power-efficient power regulation circuit for use in semiconductor circuits powered by a power signal. The power regulation circuit includes an n-channel transistor which provides a regulated power signal having a stabilized voltage level for use by the semiconductor circuit. A bias pull-up circuit is coupled to the gate of the n-channel transistor and arranged for biasing the n-channel transistor so that it normally conducts current. A resistive circuit, including a resistive element arranged in series with a resistor-arranged p-channel transistor, is coupled to a source of the n-channel transistor and, in response to the regulated power signal, provides a feedback-control signal. A voltage control circuit, coupled to the bias pull-up circuit and the resistive circuit, is activated to control the n-channel transistor in response to the feedback control signal.
The power regulation circuit described in the Casper patent provides a regulated output voltage that tracks the external voltage as the external voltage increases. Unfortunately, at low voltage, the regulated output voltage of the power regulation circuit trails behind the external voltage by approximately one threshold voltage, V.sub.T, of the n-channel transistor. This is not a problem provided that the operating voltage for the integrated circuit is sufficiently high. However, industry trends are to continue to reduce the operating voltage of integrated circuits. Thus, as the operating voltage is reduced, this inherent lag between the regulated voltage and the external voltage may cause problems with the operation of the semiconductor circuit that uses the output of the regulator.
FIG. 1 is a schematic diagram of an improvement of the voltage regulator of the Casper patent. Voltage regulator 100 includes n-channel output transistor 102 that is coupled to produce the regulated voltage labeled V.sub.CCR at a source/drain region of transistor 102. Regulator 100 further includes n-channel transistor 104 that includes a gate that is coupled to the gate of transistor 102. Transistors 102 and 104 each include a source/drain region that is coupled to an external voltage supply labeled V.sub.CCX. A second source/drain region of transistor 104 is coupled to level sensing circuit 106. Level sensing circuit 106 includes p-channel transistor 108 and voltage divider 110. Transistor 108 includes a first source/drain region that is coupled to the source/drain region of transistor 104. Transistor 108 also includes a gate that is coupled to ground. Voltage divider 110 is coupled between the second source/drain region of transistor 108 and ground.
Regulator 100 also includes n-channel transistor 112 that is coupled as a pull-down device in a feedback path to the gates of transistors 104 and 102. A gate of transistor 112 is coupled to an output of voltage divider 110 at node B. A first source/drain region of transistor 112 is coupled to ground. A second source/drain region of transistor 112 is coupled to the gates of transistors 102 and 104 to provide a reference voltage labeled V.sub.REF which is used to regulate the output of transistor 102.
Regulator 100 further includes feedback shut-off circuit 114. Circuit 114 includes voltage divider 116 that is coupled between V.sub.CCX and V.sub.REF. Circuit 114 further includes p-channel transistor 118 with a control gate coupled to an output of voltage divider 116. P-channel transistor 118 further includes a first source/drain region that is coupled to V.sub.CCX. Circuit 114 also includes n-channel transistors 120 and 122. Transistor 120 is a long-L transistor. A first source/drain region of transistor 120 is coupled to a second source/drain region of transistor 118 at node A. A second source/drain region of transistor 120 is coupled to ground and a gate of transistor 120 is coupled to V.sub.CCX. A gate of transistor 122 is coupled to node A. A first source/drain region of transistor 122 is coupled to ground and a second source/drain region of transistor 122 is coupled to the gate of transistor 112 at node B.
The improvement in regulator 100 is in the incorporation of feedback shut-off circuit 114 which turns off the feedback path of regulator 100 at voltage levels corresponding to a "burn-in" mode for the semiconductor circuit. In the burn-in mode, V.sub.CCX reaches a voltage level that causes sufficient current in voltage divider 116 so as to turn on transistor 118. Since transistor 120 is a long-L transistor, transistor 118 is able to overcome the effect of transistor 120 on node A and bring node A to a high potential so as to turn on transistor 122. When transistor 122 is turned on, node B is brought to approximately ground potential so as to turn off transistor 112 and thereby disconnect the feedback to transistors 102 and 104. By disconnecting the feedback path, the output of transistor 102 is more easily able to track increases in the external voltage V.sub.CCX. However, at low voltages, improved regulator 100 also produces the characteristic lag between V.sub.CCX and V.sub.CCR at low voltages.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a power regulation circuit that tracks the external voltage at low voltages.